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Integrated Circuit Systems, Inc.
ICS9248-87
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E type chipset. Output Features: * 2- CPUs @2.5V, up to 155MHz. * 9 - SDRAM @ 3.3V, up to 155MHz. * 8 - PCICLK @ 3.3V * 1 - IOAPIC @ 2.5V, * 2 - 3V66MHz @ 3.3V * 2- 48MHz, @3.3V fixed. * 1- 24/48MHz, @3.3V * 1- REF @3.3V, 14.318MHz. Features: * Up to 155MHz frequency support * Support FS0-FS3 strapping status bit for I2C read back. * Support power management: Power down Mode from I2C programming. * Spread spectrum for EMI control ( 0.25% center). * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: < 250ps * 3V66 - 3V66: <175ps * PCI - PCI: <500ps * For group skew specification, please refer to group timing relationships table.
Pin Configuration
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD. 1: These are double strength.
Block Diagram
PLL2
2
Functionality
48MHz /2 24_48MHz
FS3 FS2 FS1 FS0
CPU (MHz)
CPU/ SDRAM 3V66 SDRAM (MHz) (MHz)
X1 X2
XTAL OSC PLL1 Spread Spectrum
P C I C L K I OA P I C I OA P I C (PCI* (3V66* (PCI) 1/2) 1/2) (MHz) (MHz) (MHz)
REF1
CPU DIVDER
2
CPUCLK [1:0]
SDRAM DIVDER
8
SDRAM [7:0] SDRAM_F
SEL24_48# IC
2
{SDATA SCLK
FS[3:0] PD#
Control Logic
IOAPIC DIVDER
IOAPIC
Config. Reg.
PCI DIVDER
8
PCICLK [7:0]
3V66 DIVDER
3V66 [1:0]
2
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
83.3 124.00 155.00 143.96 70.00 112.00 150.00 140.00 68.33 107.00 138.00 137.33 66.80 100.30 133.60 133.60
1.00 1.00 1.00 1.33 0.67 1.00 1.00 1.33 0.67 1.00 1.00 1.33 0.67 1.00 1.00 1.33
83.3 55.48 124.00 82.67 155.00 103.33 108.00 72.00 105.00 70.00 112.00 74.67 150.00 100.00 105.00 70.00 102.50 68.33 107.00 71.33 138.00 92.00 103.00 68.67 100.20 66.80 100.30 66.80 133.60 89.07 100.20 66.80
27.74 41.33 51.67 36.00 35.00 37.33 50.00 35.00 34.17 35.67 46.00 34.34 33.40 33.40 44.53 33.40
13.87 20.67 25.83 18.00 17.50 18.67 25.00 17.50 17.08 17.83 23.00 17.17 16.70 16.70 22.27 16.70
27.74 41.33 51.67 36.00 35.00 37.33 50.00 35.00 34.17 35.67 46.00 34.34 33.40 33.40 44.53 33.40
9248-87 Rev D 10/27/00 Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9248-87
Preliminary Product Preview
General Description
The ICS9248-87 is the single chip clock solution for designs using 810/810E style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-87 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF1, X1, X2 GNDPCI, VDDPCI = PCICLK [7:0] GNDSDRAM, VDDSDRAM = SDRAM [8:0] GND3V66, VDD3V66 = 3V66 VDD48 = 48MHz, 24MHz GNDCOR, VDDCOR = supply for PLL core VDDLAPIC = IOAPIC GNDLCPU, VDDLCPU = CPUCLKL [1:0]
Pin Configuration
PIN NUMBER 1 2, 6, 16, 24, 27, 34, 42 3 4 5, 9, 13, 20, 26, 30, 38 8, 7 10 11 12 19, 18, 17, 15, 14 21, 22 23 25 28 29 31 32, 33, 35, 36, 37, 39, 40, 41 43 44, 45 46 47 48 PIN NAME REF1 FS3 VDD X1 X2 GND 3V66 [1:0] FS0 PCICLK0 FS1 PCICLK1 FS2 PCICLK2 PCICLK [7:3] 48MHz SEL24_48# 24_48MHz SDATA SCLK PD# SDRAM_F SDRAM [7:0] GNDLCPU CPUCLK [1:0] VDDLCPU IOAPIC VDDLAPIC TYPE OUT IN PWR IN OUT PWR OUT IN OUT IN OUT IN OUT OUT OUT IN OUT IN IN IN OUT OUT PWR OUT PWR OUT PWR DESCRIPTION 14.318 MHz reference clock. Frequency select pin. 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48MHz output Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Ground pin for 3V outputs. 3V66 clock outputs. Frequency select pin. PCI clock output. Frequency select pin. PCI clock output. Frequency select pin. PCI clock output. PCI clock outputs. 48MHz output clocks Sel pin for enabling 24MHz or 48MHz H=24MHz L=48MHz Clock output for super I/O/USB Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 2 SDRAM clock output - free running not affected by I C SDRAM clock outputs Ground pin for the CPU clocks. CPU clock outputs. Power pin for the CPUCLKs. 2.5V 2.5V clock output Power pin for the IOAPIC. 2.5V
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ICS9248-87
Preliminary Product Preview
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
General I2C serial interface information
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-87
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte4: Functionality and Frequency Select Register (default = 0)
Bit Bit (2, 7:4) Description CPUCLK CPU/ (MHz) SDRAM SDRAM (MHz) 3V66 (MHz) 55.48 82.67 103.33 72.00 70.00 74.67 100.00 70.00 68.33 71.33 92.00 68.67 66.80 66.80 89.07 66.80 96.67 93.33 90.67 86.67 86.00 84.67 80.67 79.33 78.00 76.00 73.33 70.00 75.33 76.67 75.33 73.33 PCICLK (MHz) 27.74 41.33 51.67 36.00 35.00 37.33 50.00 35.00 34.17 35.67 46.00 34.34 33.40 33.40 44.53 33.40 48.33 46.67 45.33 43.33 43.00 42.33 40.33 39.67 39.00 38.00 36.67 35.00 37.67 38.33 37.67 36.67 PWD IOAPIC (MHz) =PCI/2 =PCI 13.87 27.74 20.67 41.33 25.83 51.67 18.00 36.00 17.50 35.00 18.67 37.33 25.00 50.00 17.50 35.00 17.08 34.17 17.83 35.67 23.00 46.00 17.17 34.34 16.70 33.40 16.70 33.40 00100 22.27 44.53 Note1 16.70 33.40 24.17 48.33 23.33 46.67 22.67 45.33 21.67 43.33 21.50 43.00 21.17 42.33 20.17 40.33 19.83 39.67 19.50 39.00 19.00 38.00 18.33 36.67 17.50 35.00 18.83 37.67 19.17 38.33 18.83 37.67 18.33 36.67 0 1 0
Bit 2, Bit 7:4
Bit 3 Bit 1 Bit 0
0 0 0 0 0 83.3 1.00 83.3 0 0 0 0 1 124.00 1.00 124.00 0 0 0 1 0 155.00 1.00 155.00 0 0 0 1 1 143.96 1.33 108.00 0 0 1 0 0 70.00 0.67 105.00 0 0 1 0 1 112.00 1.00 112.00 0 0 1 1 0 150.00 1.00 150.00 0 0 1 1 1 140.00 1.33 105.00 0 1 0 0 0 68.33 0.67 102.50 0 1 0 0 1 107.00 1.00 107.00 0 1 0 1 0 138.00 1.00 138.00 0 1 0 1 1 137.33 1.33 103.00 0 1 1 0 0 66.80 0.67 100.20 0 1 1 0 1 100.30 1.00 100.30 0 1 1 1 0 133.60 1.00 133.60 0 1 1 1 1 133.60 1.33 100.20 1 0 0 0 0 145.00 1.00 145.00 1 0 0 0 1 140.00 1.00 140.00 1 0 0 1 0 136.00 1.00 136.00 1 0 0 1 1 130.00 1.00 130.00 1 0 1 0 0 129.00 1.00 129.00 1 0 1 0 1 127.00 1.00 127.00 1 0 1 1 0 121.00 1.00 121.00 1 0 1 1 1 119.00 1.00 119.00 1 1 0 0 0 117.00 1.00 117.00 1 1 0 0 1 114.00 1.00 114.00 1 1 0 1 0 110.00 1.00 110.00 1 1 0 1 1 105.00 1.00 105.00 1 1 1 0 0 75.33 0.67 113.00 1 1 1 0 1 153.33 1.33 115.00 1 1 1 1 0 150.63 1.33 113.00 1 1 1 1 1 146.63 1.33 110.00 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.25% Center Spread 0 - Running 1- Tristate all outputs
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 1) All entries selectable through I2C. Entries 1 -16 are also selectable through FS pins. 2) The IOAPIC Frequency change from IOAPIC=PCICLK/2 to IOAPIC=PCICLK is controlled by IOAPC_Freq control in I2C Byte 3 Bit 1, default is IOAPIC=PCICLK/2. 3) Read back code of PWD shows revision ID.
I2C is a trademark of Philips Corporation
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ICS9248-87
Preliminary Product Preview
Byte 0: Control Register Active/Inactive Register (1= enable, 0 = disable)
Byte 1: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 0 0 0 0 0 23 1 21,22 1 0
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d 24/48MHz 48MHz R e s e r ve d
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# 32 33 35 36 37 39 40 41
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
Byte 3: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# 19 18 17 15 14 12 11 10
PWD 1 1 1 1 1 1 1 1
DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 X X X 1 X 1 X
DESCRIPTION R e s e r ve d FS2# FS1# FS0# IOAPIC (SEL24_48#)# FREQ_IOAPIC =1=>IOAPIC=PCICLK/2 FREQ_IOAPIC=0=> IOAPIC= PCICLK FS3#
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 0 0 0 0 0 0 0 0
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 3. SDRAM_F is free running and cannot be turned off by I2C
Note: Dont write into this register, writing into this register can cause malfunction
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5
ICS9248-87
Preliminary Product Preview Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS924887 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the devices internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
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6
ICS9248-87
Preliminary Product Preview
Fig. 2a
Fig. 2b
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7
ICS9248-87
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-87 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-87
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table
Group CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT CPU 66MHz Offset 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance Transition Time1 Settling Time1 Clk Stabilization 1 Delay
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH
CONDITIONS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
MIN 2 VSS-0.3 -5 -5 -200
TYP
2.0 -100 60 400 14.318
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 100 600 mA A MHz nH pF pF pF mS mS mS nS nS
27
7 5 6 45 3 3 3 10 10
1 1
Guarenteed by design, not 100% tested in production.
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ICS9248-87
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 V V mA mA ns ns % ps ps
50
55 175 250
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 175 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
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ICS9248-87
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Skew
1
SYMBOL RDSP4B1 RDSN4B1 VOH4\B VOL4B IOH4B IOL4B tr4B1 tf4B1 dt4B1 tjcyc-cyc Tsk41 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.0 V, VOH@ MAX = 2.375 V VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 9 9 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 30 30 0.4 -27 30 1.6 1.6 55 500 250 V V mA mA ns ns % ps ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 Tr31 Tf3 Dt3
1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
Tsk3 tj cyc-cyc
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
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ICS9248-87
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 500 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Skew
1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr51 tf5
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks VT = 1.5 V
MIN 20 20 2.4 -29 29
TYP
MAX UNITS 60 60 0.4 -23 27 V V mA mA nS nS % pS pS pS
1.8 1.7 45
4 4 55 500 1000 250
dt5
tjcyc-cyc1 tjcyc-cyc1 Tsk
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9248-87
Preliminary Product Preview
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 48
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 15.748 MAX 16.002 MIN .620
D (inch) MAX .630
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9248yF-87
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
13
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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